This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-198551, filed on Jun. 29, 2001; the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device and its manufacturing method, and more particularly, it relates to a trench MOS (Metal-Oxide-Semiconductor) gate structure and a method of manufacturing it.
A trench structure where trenches formed in semiconductor are utilized is applied to semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the structure has been recognized as being advantageous especially for a use in relation with supply and control of electric power. For instance, IGBT of the trench structure has both the properties of high level input impedance peculiar to MOSFETs and low saturation voltage unique to bipolar transistors, and it has been used in a wide range including blackout-free power supply, various motor driver unit, and so forth.
FIG. 13 is a perspective view showing a vertical IGBT having a trench gate structure which was attempted by the Inventor of the present invention in the course of attaining this invention. A structure in FIG. 13 of the trench IGBT will be outlined in terms of its manufacturing process.
First, a p-type base layer 102 is formed in the surface of an n-type base layer 101 by means of diffusion, and the resultant surface is selectively superposed with an n-type source layer 103 by diffusion. Then, after trenches T for MOS gates are formed, they are covered with a gate insulation film 104 and embedded with gate electrodes 105, which is further superimposed with an insulation film 111 to isolate the gate electrodes at their respective tops. After that, windows are formed to create open contact regions, and then, an emitter electrode 107 is created at the top. In the reverse or bottom side of the integrated substrate, a collector electrode 109 underlies a p-type emitter layer 108 to attain a trench-type IGBT structure.
In the trench MOS gate structure obtained in this manner, the n-type source layer 103 is shaped in a lattice pattern so as to electrically connect the emitter electrode 107 to the n-type source layer 103. Such a xe2x80x9clatticexe2x80x9d pattern is useful in maximizing a MOS channel width and reducing an ON-resistance in the resultant device.
In the case of the IGBT shown in FIG. 13, however, an increase in the MOS channel width leads to a rise of saturation current Icp, which in turn causes a reduction in durability against load short-circuit.
As will be recognized, the trench IGBT shown in FIG. 13 should have the lattice-shaped n-type source pattern to reduce the ON-voltage, and this results in the saturation current Icp being raised to eventually decrease the durability against short-circuit.
According to an embodiment of the invention, there is provided a semiconductor device comprising a base layer of a first conductivity type, a base layer of a second conductivity type created over the base layer of the first conductivity type, trenches each defined to penetrate the base layer of the second conductivity type and reach the base layer of the first conductivity type, a source layer of the first conductivity type selectively formed in the base layer of the second conductivity type, a channel layer of the second conductivity located between the base layer of the second conductivity and the trenches, having a higher impurity concentration level compared with the base layer of the second conductivity type, a gate insulation film covering inner wall surfaces of the trenches, gate electrodes located on the channel layer of the second conductivity type with an interposition of the gate insulation film between them, and a first primary electrode electrically connected to both the source layer of the first conductivity type and the base layer of the second conductivity type, and the channel layer of the second conductivity type has a generally uniform distribution of impurity concentration along depths of the trenches.
With the architecture as stated above, saturation current Icp can be reduced without a decrease in ON-resistance of the device so as to permit the device to have a sufficiently large durability against short-circuit.